Re: File modification on the fly (Verilog)

Parsing Verilog files can be tricky, and you should probably use a parser: Verilog-Perl. But, this might work for simple files:

use warnings;
use strict;

# Change input record separator to parse whole Verilog lines
local $/ = ';';
while (<DATA>) {
    s/\s+/ /g;    # Convert all whitespace to single-space
    print "$_\n";
}

__DATA__
 DFFX1 k0_reg_184  ( .D(key_184 ), .CLK(clk), .QN(n18736) );
DFFX1 k0_reg_183  ( .D(key_183 ), .CLK(clk), .Q(k0_183 ), .QN(n65993)
         );
[download]

Output:

 DFFX1 k0_reg_184 ( .D(key_184 ), .CLK(clk), .QN(n18736) );
 DFFX1 k0_reg_183 ( .D(key_183 ), .CLK(clk), .Q(k0_183 ), .QN(n65993) 
+);
[download]

Comment on Re: File modification on the fly (Verilog) Select or Download Code

Replies are listed 'Best First'.
Re^2: File modification on the fly (Verilog) by mavericknik (Sexton) on Aug 02, 2016 at 21:43 UTC
Thank you so much for your help, I works perfectly. If I understand your script correctly, you are setting the line delimiter to a ";" and replacing all multiple spaces to single spaces? I have parsed the netlist using verilog-perl, but the time requirement seems to increase exponentially with number of cells. For older netlists with ~5k cells, the script takes about 12 hours. With my new netlist of about 450000 cells, I'm estimating a runtime of about 200 days which is unacceptable so I'm looking at alternative approaches.	[reply]
Re^3: File modification on the fly (Verilog) by toolic (Bishop) on Aug 03, 2016 at 13:12 UTC
Thank you so much for your help You're welcome. If I understand your script correctly, you are setting the line delimiter to a ";" Yes. and replacing all multiple spaces to single spaces? \s refers to all types of whitespace; refer to perlre. The key here is that \s includes the newline character (\n). So, \s+ replaces multiple adjacent spaces, tabs and newlines. s///g changes all whitespace on a line. For older netlists with ~5k cells, the script takes about 12 hours. That is a surprisingly long time. Can you post your code for that?	[reply]
Re^3: File modification on the fly (Verilog) by $h4X4_\|=73}{ (Monk) on Aug 03, 2016 at 07:46 UTC
Depending on how your program works you can maybe gain some speed from using auto flush `$\| = 1;`. OUTPUT_AUTOFLUSH	[reply] [d/l]


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