RTL module

module top;
   buff b0 ();
endmodule

module buff (buf_in, buf_out);
   input buf_in;
   inout out;
   `ifdef SYNTHESIS
   wire  a;
   `endif
   inv i0 (.in(buf_in), .out(a      ));
   inv i1 (.in(a     ), .out(buf_out));
endmodule

module inv (in, out);
   input  in;
   output out;
   assign out = ~in;
endmodule
[download]

Sample Perl code

#!/usr/bin/env perl
use Verilog::Netlist;

    # Setup options so files can be found
    use Verilog::Getopt;
    my $opt = new Verilog::Getopt;
    $opt->parameter( "+incdir+verilog",
                     "-y","verilog",
                     );

    # Prepare netlist
    my $nl = new Verilog::Netlist (options => $opt,);
    foreach my $file ('top.v') {
        $nl->read_file (filename=>$file);
    }
    # Read in any sub-modules
    $nl->link();
    #$nl->lint();  # Optional, see docs; probably not wanted
    $nl->exit_if_error();

    foreach my $mod ($nl->top_modules_sorted) {
        show_hier ($mod, "  ", "", "");
    }

    sub show_hier {
        my $mod = shift;
        my $indent = shift;
        my $hier = shift;
        my $cellname = shift;
        if (!$cellname) {$hier = $mod->name;} #top modules get the des
+ign name
        else {$hier .= ".$cellname";} #append the cellname
        printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier);
        foreach my $sig ($mod->ports_sorted) {
            printf ($indent."     %sput %s\n", $sig->direction, $sig->
+name);
        }
        foreach my $cell ($mod->cells_sorted) {
            printf ($indent. "    Cell %s\n", $cell->name);
            foreach my $pin ($cell->pins_sorted) {
                printf ($indent."     .%s(%s)\n", $pin->name, $pin->ne
+tname);
            }
            show_hier ($cell->submod, $indent."  ", $hier, $cell->name
+) if $cell->submod;
        }
    }
[download]

I am unable to get where the `ifdef is defined.

You need to clarify what you're looking for. This is what I get when I run your code:

  Module top                                  top
      Cell b0
    Module buff                               top.b0
         input buf_in
         inoutput out
        Cell i0
         .in(buf_in)
         .out(a)
      Module inv                              top.b0.i0
           input in
           output out
        Cell i1
         .in(a)
         .out(buf_out)
      Module inv                              top.b0.i1
           input in
[download]

What output do you expect to get?

Keep in mind that there is a forum on veripool.

Thanks!! did not know veripool has a forum. Asked the question there. Will post back if i find anything.

I am looking for creating something like AUTO_TEMPLATE for emacs using perl so that i am not dependent on any editor.