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Re^3: how to preserve `defines in verilog -perl

by toolic (Bishop)
on Sep 21, 2016 at 12:19 UTC ( [id://1172298]=note: print w/replies, xml ) Need Help??


in reply to Re^2: how to preserve `defines in verilog -perl
in thread how to preserve `defines in verilog -perl

I am unable to get where the `ifdef is defined.
You need to clarify what you're looking for. This is what I get when I run your code:
Module top top Cell b0 Module buff top.b0 input buf_in inoutput out Cell i0 .in(buf_in) .out(a) Module inv top.b0.i0 input in output out Cell i1 .in(a) .out(buf_out) Module inv top.b0.i1 input in

What output do you expect to get?

Keep in mind that there is a forum on veripool.

Replies are listed 'Best First'.
Re^4: how to preserve `defines in verilog -perl
by justrajdeep (Novice) on Sep 21, 2016 at 14:25 UTC
    Thanks!! did not know veripool has a forum. Asked the question there. Will post back if i find anything.

    I am looking for creating something like AUTO_TEMPLATE for emacs using perl so that i am not dependent on any editor.

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