# Bind
 ::d::autoBindmap $intfcName 

-------------so many other lines------------------------------

############ Power information for vdd #####################
#----------------------------
 #pg_vdd s100
#----------------------------
 #Add pg_vdd_dl interface
set  intfcName pg_vdd 1.0 s 100

 #Add Verilog port binding for vss
 ::d::autoBindmap $module pg_vdd $intfcName
{
 VDD vss_dl;
 }

-----------------------so many other lines-------------------------------