Startpoint: sdram_clk (clock source 'SDRAM_CLK')
  Endpoint: sd_DQ_out[6]
            (output port clocked by SD_DDR_CLK)
  Path Group: COMBO
  Path Type: max

  Point                                       Fanout       Cap     Trans      Incr       Path
  ----------------------------------------------------------------------------------------------
  clock SDRAM_CLK (fall edge)                                             3.750000   3.750000
  sdram_clk (in)                                                0.184922  0.065438 & 3.815438 f
  sdram_clk (net)                              17     0.124019            0.000000   3.815438 f
  I_SDRAM_TOP/sdram_clk (SDRAM_TOP)                                       0.000000   3.815438 f
  I_SDRAM_TOP/sdram_clk (net)                         0.124019            0.000000   3.815438 f
  I_SDRAM_TOP/I_SDRAM_IF/sdram_clk (SDRAM_IF)                             0.000000   3.815438 f
  I_SDRAM_TOP/I_SDRAM_IF/sdram_clk (net)              0.124019            0.000000   3.815438 f
  I_SDRAM_TOP/I_SDRAM_IF/bufbdf_G1B1I16/I (bufbd7)              0.187810  0.013919 & 3.829357 f
  I_SDRAM_TOP/I_SDRAM_IF/bufbdf_G1B1I16/Z (bufbd7)              0.233113  0.210904 & 4.040261 f
  I_SDRAM_TOP/I_SDRAM_IF/sdram_clk_G1B1I16 (net)    45 0.175550           0.000000   4.040261 f
  I_SDRAM_TOP/I_SDRAM_IF/sd_mux_dq_out_6/S (mx02d4)             0.234098  0.003310 & 4.043571 f
  I_SDRAM_TOP/I_SDRAM_IF/sd_mux_dq_out_6/Z (mx02d4)             0.999121  0.776377   4.819948 f
  I_SDRAM_TOP/I_SDRAM_IF/sd_DQ_out[6] (net)     1     0.475020            0.000000   4.819948 f
  I_SDRAM_TOP/I_SDRAM_IF/sd_DQ_out[6] (SDRAM_IF)                          0.000000   4.819948 f
  I_SDRAM_TOP/sd_DQ_out[6] (net)                      0.475020            0.000000   4.819948 f
  I_SDRAM_TOP/sd_DQ_out[6] (SDRAM_TOP)                                    0.000000   4.819948 f
  sd_DQ_out[6] (net)                                  0.475020            0.000000   4.819948 f
  sd_DQ_out[6] (out)                                            0.999121  0.010237 & 4.830185 f
  data arrival time                                                                  4.830185

  clock SD_DDR_CLK (rise edge)                                            7.500000   7.500000
  clock network delay (ideal)                                             1.598546   9.098545
  clock uncertainty                                                       -0.100000  8.998545
  output external delay                                                   -2.000000  6.998545
  data required time                                                                 6.998545
  ----------------------------------------------------------------------------------------------
  data required time                                                                 6.998545
  data arrival time                                                                  -4.830185
  ----------------------------------------------------------------------------------------------
  slack (MET)                                                                        2.168359

##</code><code>##

  clock SDRAM_CLK
  sdram_clk
  sdram_clk
  I_SDRAM_TOP/sdram_clk
  I_SDRAM_TOP/sdram_clk
  I_SDRAM_TOP/I_SDRAM_IF/sdram_clk
  I_SDRAM_TOP/I_SDRAM_IF/sdram_clk
  I_SDRAM_TOP/I_SDRAM_IF/bufbdf_G1B1I16/I
  I_SDRAM_TOP/I_SDRAM_IF/bufbdf_G1B1I16/Z
  I_SDRAM_TOP/I_SDRAM_IF/sdram_clk_G1B1I16
  I_SDRAM_TOP/I_SDRAM_IF/sd_mux_dq_out_6/S
  I_SDRAM_TOP/I_SDRAM_IF/sd_mux_dq_out_6/Z
  I_SDRAM_TOP/I_SDRAM_IF/sd_DQ_out[6]
  I_SDRAM_TOP/I_SDRAM_IF/sd_DQ_out[6]
  I_SDRAM_TOP/sd_DQ_out[6]
  I_SDRAM_TOP/sd_DQ_out[6]
  sd_DQ_out[6]
  sd_DQ_out[6]