$date
	Fri Aug  1 17:33:57 2014

$end
$version
	ncsim 08.20-s012
$end
$timescale
	1ps
$end
$scope module system $end
$scope module soc $end
$scope module newton_analog_atop $end
$var wire 1 ! BBPLL_CLKO_DIG_96M $end
$var wire 1 " CKO_HFOSC_2DIV12 $end
$var wire 1 # CLKO_RXADC_96M $end
$var wire 1 $ VBGOK_H $end
$var wire 1 % YOUT_RC_CAL $end
$var wire 1 & YOUT_RC_CAL_PGA $end
$var wire 1 ' ABB_BIAS_EN $end
$var wire 1 ( TXMIX_EN $end
$var wire 1 ) XO32K_VCOUT $end
$var wire 3 * AGC_IF_CAP [2:0] $end
$var wire 2 + BBAGC_AVWIN [1:0] $end
$upscope $end
$upscope $end
$upscope $end
$scope module system $end
$scope module soc $end
$scope module newton_analog_atop $end
$var wire 3 * AGC_IF_CAP [2:0] $end
$var wire 2 + BBAGC_AVWIN [1:0] $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$dumpvars
x!
bxx +
x#
x'
x(
x$
x)
bxxx *
x"
x%
x&
$end
$dumpoff $end
 

##</code><code>##

 
V0 (BBPLL_CLKO_DIG_96M 0) vsource type=pwl wave=[ 0p 0 199p 0 200p VDD/2 399p VDD/2 400p 0 599p 0 600p VDD/2 ...... ]
V1 (CKO_HFOSC_2DIV12 0) vsource type=pwl wave=[0p 0]
V2 (CLKO_RXADC_96M 0) vsource type=pwl wave=[0p 0]
V3 (VBGOK_H 0) vsource type=pwl wave=[0p 0]
V4 (YOUT_RC_CAL 0) vsource type=pwl wave=[0p 0]
V5 (YOUT_RC_CAL_PGA 0) vsource type=pwl wave=[0p 0]
V6 (ABB_BIAS_EN 0) vsource type=pwl wave=[0p VDD/2]
V7 (TXMIX_EN 0) vsource type=pwl wave=[0p 0]
V8 (XO32K_VCOUT 0) vsource type=pwl wave=[0p z]
V9 (AGC_IF_CAP\<0\> 0) vsource type=pwl wave=[0p VDD/2]
V10 (AGC_IF_CAP\<1\> 0) vsource type=pwl wave=[0p VDD/2]
V11 (AGC_IF_CAP\<2\> 0) vsource type=pwl wave=[0p VDD/2]
V12 (BBAGC_AVWIN\<0\> 0) vsource type=pwl wave=[0p 0]
V13 (BBAGC_AVWIN\<1\> 0) vsource type=pwl wave=[0p VDD/2]