use warnings;
use strict;
use Verilog::VCD qw(:all);

my $vcd= parse_vcd('sample.vcd');
for my $code (keys %{ $vcd }) {
    for my $net (@{ $vcd->{$code}->{nets} }) {
        print "$net->{name}\n";
        for my $aref (@{ $vcd->{$code}{tv} }) {
            print "@{ $aref }\n";
        }
    }
}