# Bind
 ::d::autoBindmap $intfcName 

-------------so many other lines------------------------------
############ Power information for vss #####################
#----------------------------
 #pg_vss s100
#----------------------------
 #Add pg_vss_dl interface
set  intfcName pg_vss 1.0 s 100

 #Add Verilog port binding for vss
 ::d::autoBindmap $module pg_vss $intfcName
{
 VSSGND vss_dl;
 }

############ Power information for vdd #####################
#----------------------------
 #pg_vdd s100
#----------------------------
 #Add pg_vdd_dl interface
set  intfcName pg_vdd 1.0 s 100

 #Add Verilog port binding for vss
 ::d::autoBindmap $module pg_vdd $intfcName
{
 VDD vss_dl;
 }

-----------------------so many other lines-------------------------------

 #write component 
 ::d::writeLib $module 

##</code><code>##

 my $rpow;

for $rpow (@remove_power_list) {
    
        my $bf_content;
        open $bf_content, '+<', $bf_bind;
                  
           my $count = 0;

        while (<$bf_content>){
            
                  if($_ =~ /Power\s+information\s+for\s+$rpow\s+/) {
                $count = $. + 11; 
                }   
                    
                else    
         {   
        if($count != 0 && $. < $count)
          {   

            }   
        elsif($count != 0 && $. == $count)
          {   
             $count =0; 
              }   
         else
          {   
             print $bf_content $_; 
              }   
         }

        }             
close $bf_content;
}

##</code><code>##

 # Bind
 ::d::autoBindmap $intfcName 

-------------so many other lines------------------------------

############ Power information for vdd #####################
#----------------------------
 #pg_vdd s100
#----------------------------
 #Add pg_vdd_dl interface
set  intfcName pg_vdd 1.0 s 100

 #Add Verilog port binding for vss
 ::d::autoBindmap $module pg_vdd $intfcName
{
 VDD vss_dl;
 }

-----------------------so many other lines-------------------------------