use warnings;
use strict;


while(<DATA>){
  print unless/^#+?\s.+vss #+?$/sm .. /\}/; 
}

__DATA__

 # Bind
 ::d::autoBindmap $intfcName 

-------------so many other lines------------------------------
############ Power information for vss #####################
#----------------------------
 #pg_vss s100
#----------------------------
 #Add pg_vss_dl interface
set  intfcName pg_vss 1.0 s 100

 #Add Verilog port binding for vss
 ::d::autoBindmap $module pg_vss $intfcName
{
 VSSGND vss_dl;
 }

############ Power information for vdd #####################
#----------------------------
 #pg_vdd s100
#----------------------------
 #Add pg_vdd_dl interface
set  intfcName pg_vdd 1.0 s 100

 #Add Verilog port binding for vss
 ::d::autoBindmap $module pg_vdd $intfcName
{
 VDD vss_dl;
 }

-----------------------so many other lines-------------------------------

 #write component 
 ::d::writeLib $module