input abc10;

output v;

checkinst_0(
.port1(wireY),
.port2(wireZ),
.port3(wireX),
.port4(port711),
.port10
);

checkinst_2(
.port5(wireYx),
.port6(wireZ),
.port7(wireaX),
.port8(abc10),
.port11
);

checkinst_3(
.port5(wireYd),
.port6(wireZS),
.port7(wireXW),
.port8(port10),
.port12
);