use Verilog::Netlist::Net;
sub Verilog::Netlist::Net::my_dump_drivers { 
    my $self = shift;
    my $indent = shift||0;
    my @ret;
    push @ret, " "x$indent,"Net:",$self->name,"\n";
   
    
    if (my $port = $self->port) {
	push @ret, " "x$indent,"  Port: ",$port->name,"  ",$port->direction,"\n";
    }
    foreach my $cell ($self->module->cells_sorted) {
	foreach my $pin ($cell->pins_sorted) {
	    if ($pin->port && $pin->net && $pin->net == $self) {
		push @ret, " "x$indent,"  Pin:  ",$cell->name,".",$pin->name
		    ,"  ",$pin->port->direction,"\n";
	    }
	    elsif ($pin->net && $self->name eq $pin->net->name) {
		push @ret, "%Warning: Internal net name duplicate: ".$cell->name."  ".$self->name."\n"
		    .$self->comment."  ".$pin->net->comment."\n"
		    ."$self  ".$pin->net->name."\n";
	    }
	}
    }
 return @ret;
}