#!/usr/bin/perl
# This is a complete verilog pre-parser!
# For a command line version, see vppreproc
use Verilog::Getopt;
use Verilog::Preproc;
 
my $opt = new Verilog::Getopt;
@ARGV = $opt->parameter(@ARGV);
 
my $vp = Verilog::Preproc->new(options=>$opt,);
$vp->open(filename=>"../common/tiri_defines.vh");
while (defined (my $line = $vp->getline())) {
   print $line;
}

sub define {
   my $self = shift;
   my $defname = shift;
   my $value = shift;
   my $params = shift;

   print "defname = $defname\n";
   print "  value = $value\n";
   print " params = $params\n";
}

sub def_exists  {
   my $self = shift;
   my $defname = shift;
   print "DEF_EXISTS\n";
}