use warnings FATAL => 'all';
use strict;
use Verilog::VCD qw(parse_vcd);

my $file = shift;
my $vcd  = parse_vcd($file);

for my $code (keys %{ $vcd }) {
    my $name  = "$vcd->{$code}{nets}[0]{hier}.$vcd->{$code}{nets}[0]{name}";
    my $times = @{ $vcd->{$code}{tv} };
    for my $aref (@{ $vcd->{$code}{tv} }) {
        print "$name @{ $aref }\n";
    }
}

__END__

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