##Staring of org_lib.lib library_for_dev_47nm_proj { lu_table_template(t4x3) { variable_1: total_output_net_capacitance ; variable_2: input_net_transistion ; index_1 {\u201c5, 20, 60, 200\u201d} ; index_2 {\u201c0.01, 0.1, 2.0\u201d} ; } cell(and2_f2) { cell_type : combo; cell_function : A * B; timing_const : NIL; clock_present : NIL; leakage_power() { power_pin : "VDD" ; when : "!A&!B" ; value : "0.000047" ; } pin(A1) { direction : input; capacitance : 2.141; } pin(B1) { direction : input; capacitance : 1.948; } pin(Y) { direction : output; function : "A1 * B1"; } } cell(nand2_f2) { area : 359.1; cell_type : combo; cell_function : (A1 * B1)\u201; clock_present : NIL; leakage_power() { power_pin : "VDD" ; when : "!A&B" ; value : "0.00057" ; } pin(A1) { direction : input; capacitance : 12.547; } pin(B1) { direction : input; capacitance : 12.259; } pin(O) { direction : output; function : "(A1 * B1)\u2019"; } } cell(dfr_f5) { area : 4819.5; timing_const : YES; clock_present : YES; leakage_power() { power_pin : "VDD" ; when : "D" ; value : "5.00057" ; } ff(IQ,IQN) { next_state : "DATA1"; clocked_on : "CLK2\u2019"; clear : "RST3\u2019"; } pin(DATA1) { direction : input; capacitance : 51.289; } pin(CLK2) { direction : input; capacitance : 52.305; } pin(RST3) { direction : input; capacitance : 28.602; } pin(Q) { direction : output; function : "IQ"; } } }