module top;
   buff b0 ();
endmodule

module buff (buf_in, buf_out);
   input buf_in;
   inout out;
   `ifdef SYNTHESIS
   wire  a;
   `endif
   inv i0 (.in(buf_in), .out(a      ));
   inv i1 (.in(a     ), .out(buf_out));
endmodule

module inv (in, out);
   input  in;
   output out;
   assign out = ~in;
endmodule