UVM_INFO @1091277 reporter [Z7_COREB]: WR8: A=fc03c002 W=08 R=08; T=1091277
UVM_INFO @1091528 reporter [Z7_COREB]: pre_main: Inserting random delay through asm nops, random loop count is  00000009; T=1091528
UVM_INFO @1092507 reporter [Z4_COREA]: mti_clk_chk: ################ start of test ################ ; T=1092507
UVM_INFO @1092563 reporter [Z4_COREA]: mti_clk_chk: Checking the period of MTI, MTI10 clk from SV; T=1092563
UVM_INFO @1092598 reporter [Z4_COREA]: C FLAG_SET: Setting flag 1; T=1092598
UVM_INFO @1092598 reporter [Z4_COREA]: V FLAG_WAIT: Received flag 1; T=1092598
UVM_INFO @1092598 reporter [testbench.top_level_module.\mti_clk_chk::main ]:  Checking period of MTI CLk; T=1092598
UVM_INFO @1092605 /proj/rru2_verif/usr/Tilak/SV_UVM/testbench/data_ipdss/v_ms_mti_stim_vip/testbench/classes_v/mti_clk_chk.sv(147) uvm_test_top.default_env.default_sequencer[100]@@mti_clk_chk [mti_clk_chk:INFO]: Period value of MTI Clock: 3.125000 ns; T=1092605
UVM_INFO @1092605 reporter [testbench.top_level_module.\mti_clk_chk::main ]: MTI Clock is being generated correctly ; T=1092605
UVM_INFO @1092605 reporter [testbench.top_level_module.\mti_clk_chk::main ]:  Checking period of MTI10 CLk; T=1092605
UVM_INFO @1092634 reporter [Z4_COREA]: C FLAG_WAIT: Checking flag 2, status is 0; T=1092634
UVM_INFO @1092655 /proj/rru2_verif/usr/Tilak/SV_UVM/testbench/data_ipdss/v_ms_mti_stim_vip/testbench/classes_v/mti_clk_chk.sv(165) uvm_test_top.default_env.default_sequencer[100]@@mti_clk_chk [mti_clk_chk:INFO]: Period value of MTI10 Clock: 31.250000 ns; T=1092655
UVM_INFO @1092655 reporter [testbench.top_level_module.\mti_clk_chk::main ]: MTI10 Clock is being generated correctly ; T=1092655
UVM_INFO @1092655 reporter [Z4_COREA]: V FLAG_CLEAR: Clearing flag 1; T=1092655
UVM_INFO @1092655 reporter [Z4_COREA]: V FLAG_SET: Setting flag 2; T=1092655
UVM_INFO @1092655 reporter [Z4_COREA]: V FLAG_WAIT: Checking flag 3, status is 0; T=1092655
UVM_INFO @1092655 reporter [Z4_COREA]: V FLAG_WAIT: Received flag 2; T=1092655
UVM_INFO @1092655 reporter [Z4_COREA]: V FLAG_WAIT: Checking flag 2, status is 1; T=1092655
UVM_INFO @1092738 reporter [Z4_COREA]: C FLAG_WAIT: Checking flag 2, status is 1; T=1092738
UVM_INFO @1092850 reporter [Z4_COREA]: mti_clk_chk:  All clock period Checking done; T=1092850
UVM_INFO @1092886 reporter [Z4_COREA]: C FLAG_SET: Setting flag 3; T=1092886
UVM_INFO @1092886 reporter [Z4_COREA]: V FLAG_WAIT: Received flag 3; T=1092886
UVM_INFO @1092886 /proj/rru2_verif/usr/Tilak/SV_UVM/testbench/data_ipdss/v_ms_mti_stim_vip/testbench/classes_v/mti_clk_chk.sv(186) uvm_test_top.default_env.default_sequencer[100]@@mti_clk_chk [mti_clk_chk:INFO]: ************************  SV END******************** ; T=1092886
UVM_INFO @1092886 reporter [testbench.top_level_module.\mti_clk_chk::main ]: END OF execute; T=1092886
UVM_INFO @1092886 reporter [Z4_COREA]: V FLAG_WAIT: Received flag 3; T=1092886
UVM_INFO @1092886 reporter [Z4_COREA]: V FLAG_WAIT: Checking flag 3, status is 1; T=1092886
UVM_INFO @1092906 reporter [Z7_COREB]: DUMMY: Hi this is CORE2  ; T=1092906
UVM_INFO @1093261 reporter [Z4_COREA]: W8: A=0100fe00 W=80; T=1093261
[testbench.tb_aux_vip.GET_RANDOM_GEN.genblk1[2].TB_AUX_GET_RANDOM_32]     1
[testbench.top.rru2_top.pmc.A_IP_VREF_CLN16FFC]    11
[testbench.top_level_module.\mti_clk_chk::main ]     7
[testbench.unnamed$$_22]     1
[testbench.unnamed$$_23]     4
[testbench.unnamed$$_26]     3
[uvm_test_top]     2
[uvm_test_top.uvm_fuse_load_manager_inst]   215
UVM_INFO @1130797 END_SIM: Testcases completed Total= 1; T=1130797
UVM_INFO @1130797 END_SIM: Testcases completed Successfully= 1; T=1130797
UVM_INFO @1130797 END_SIM: Testcases with Warnings= 0; T=1130797