Data from LOG1:

INFO @1102372 mti_clk_chk:  Checking period of MTI CLk; T=1102372
INFO @1102377 mti_clk_chk: Period value of MTI Clock: 3.125000 ns; T=1102377
INFO @1102377 mti_clk_chk: MTI Clock is being generated correctly ; T=1102377
INFO @1102377 mti_clk_chk:  Checking period of MTI10 CLk; T=1102377
INFO @1102418 mti_clk_chk: Period value of MTI10 Clock: 31.250000 ns; T=1102418
INFO @1102418 mti_clk_chk: MTI10 Clock is being generated correctly ; T=1102418
INFO @1148661 mti_clk_chk: C-Code exit execution. code=<aa>; T=1148661
INFO @1148661 mti_clk_chk: ************************  SV END******************** ; T=1148661
INFO @1148661 testbench.soc_monitors_inst: DMA multi loop check start; T=1148661
INFO @1148661 testbench.soc_monitors_inst.ASSERT_IPD_REQ_PERIPH_DMA_CH_MUX_0: Assertion ASSERT_IPD_REQ_PERIPH_DMA_CH_MUX_0 PASSED; T=1148661
INFO @1148661 testbench.soc_monitors_inst.ASSERT_IPD_REQ_PERIPH_DMA_CH_MUX_1: Assertion ASSERT_IPD_REQ_PERIPH_DMA_CH_MUX_1 PASSED; T=1148661
INFO @1148661 mti_lane2_bw_mon: total bytes = 0, at time = 1148661; T=1148661
INFO @1148661 mti_lane2_bw_mon: time window = 0, at time = 1148661; T=1148661
INFO @1148661 mti_lane2_bw_mon: BW in Mbps = 0, at time = 1148661; T=1148661
INFO @1148662 END_TESTCASE: Warns= 0; T=1148662
INFO @1148662 END_TESTCASE: Errors= 0; T=1148662
INFO @1148662 END_TESTCASE: Fatals= 0; T=1148662
INFO @1148662 END_TESTCASE:    TESTCASE PASS    ; T=1148662
INFO @1148662 END_TESTCASE: Testcase completed Successfully; T=1148662

Data from LOG 2:

UVM_INFO @1092598 reporter [testbench.top_level_module.\mti_clk_chk::main ]:  Checking period of MTI CLk; T=1092598
UVM_INFO @1092605 /proj/rru2_verif/usr/Tilak/SV_UVM/testbench/data_ipdss/v_ms_mti_stim_vip/testbench/classes_v/mti_clk_chk.sv(147) uvm_test_top.default_env.default_sequencer[100]@@mti_clk_chk [mti_clk_chk:INFO]: Period value of MTI Clock: 3.125000 ns; T=1092605
UVM_INFO @1092605 reporter [testbench.top_level_module.\mti_clk_chk::main ]: MTI Clock is being generated correctly ; T=1092605
UVM_INFO @1092605 reporter [testbench.top_level_module.\mti_clk_chk::main ]:  Checking period of MTI10 CLk; T=1092605
UVM_INFO @1092655 /proj/rru2_verif/usr/Tilak/SV_UVM/testbench/data_ipdss/v_ms_mti_stim_vip/testbench/classes_v/mti_clk_chk.sv(165) uvm_test_top.default_env.default_sequencer[100]@@mti_clk_chk [mti_clk_chk:INFO]: Period value of MTI10 Clock: 31.250000 ns; T=1092655
UVM_INFO @1092655 reporter [testbench.top_level_module.\mti_clk_chk::main ]: MTI10 Clock is being generated correctly ; T=1092655
UVM_INFO @1092886 /proj/rru2_verif/usr/Tilak/SV_UVM/testbench/data_ipdss/v_ms_mti_stim_vip/testbench/classes_v/mti_clk_chk.sv(186) uvm_test_top.default_env.default_sequencer[100]@@mti_clk_chk [mti_clk_chk:INFO]: ************************  SV END******************** ; T=1092886
UVM_INFO @1092886 reporter [testbench.top_level_module.\mti_clk_chk::main ]: END OF execute; T=1092886
[testbench.tb_aux_vip.GET_RANDOM_GEN.genblk1[2].TB_AUX_GET_RANDOM_32]     1
[testbench.top.rru2_top.pmc.A_IP_VREF_CLN16FFC]    11
[testbench.top_level_module.\mti_clk_chk::main ]     7
[testbench.unnamed$$_22]     1
[testbench.unnamed$$_23]     4
[testbench.unnamed$$_26]     3
[uvm_test_top]     2
[uvm_test_top.uvm_fuse_load_manager_inst]   215
UVM_INFO @1130797 END_SIM: Testcases completed Total= 1; T=1130797
UVM_INFO @1130797 END_SIM: Testcases completed Successfully= 1; T=1130797