11:57_dcollins_HOME_[267]>./tk_verilog.pl
HL: no_gated_clk_cts_1:no_gated_clk_cts_1:
5 : clk_cts
DEBUG: no_gated_clk_cts_1:no_gated_clk_cts_1:clk_cts:no_gated_clk_cts_1:0
DC:cts_env_1,cts_inst,y,
DC:cts_env_1,cts2_inst,y,
DC:cts_env_3,cts3_inst,y,