input [31:0] 		  ucast_mem_wdata;
   input [31:0] 		  ucast_mem_wren;
   input 			  ucast_mem_wr;
   input 			  ucast_mem_rd;
   output [31:0] 		  ucast_mem_rdata;

   wire [BMU_MEM_ADDR_BITS-1:0]   mem_addr; always @ (posedge sys_clk or negedge sys_reset_n)
     begin
	if (!sys_reset_n)
	  ucast_int_mem_rd_r <= 0;
	else
	  ucast_int_mem_rd_r <= ucast_int_mem_rd &amp; !ucast_access;
     end


endmodule