use strict;
use warnings;

my @ins;
my @outs;
my @blocks;
my $flag = 0;
while (<DATA>) {
    if (/\binput\b/)  { push @ins , $_ }
    if (/\boutput\b/) { push @outs, $_ }
    if (/\balways\b/) {
        s/^.*\b(always)\b/$1/;
        push @blocks, $_;
        $flag = 1;
        next;
    }
    if ($flag) {
        push @blocks, $_;
        $flag = 0 if (/^\s*$/); # blank line ends always block
    }
}

create_file('inputs.v' , @ins);
create_file('outputs.v', @outs);
create_file('always.v' , @blocks);

sub create_file {
    my $file = shift;
    open my $fileHandle, '>', $file or die "Unable to create $file: $!\n";
    print $fileHandle $_ for (@_);
    close $fileHandle or die "Unable to close file $file: $!\n";
}

__DATA__
   input [31:0] 		  ucast_mem_wdata;
   input [31:0] 		  ucast_mem_wren;
   input 			  ucast_mem_wr;
   input 			  ucast_mem_rd;
   output [31:0] 		  ucast_mem_rdata;

   wire [BMU_MEM_ADDR_BITS-1:0]   mem_addr; always @ (posedge sys_clk or negedge sys_reset_n)
     begin
	if (!sys_reset_n)
	  ucast_int_mem_rd_r <= 0;
	else
	  ucast_int_mem_rd_r <= ucast_int_mem_rd & !ucast_access;
     end


endmodule