#!/usr/bin/perl
use Verilog::Netlist;
# set up options so that files can be found
use Verilog::Getopt;
#push(@INC,'pwd');
my $opt=new Verilog::Getopt;
$opt->parameter("-y","i2c",);

# prepare netlist
#$file='home/vp/roopa/i2c/i2c_master_byte_ctrl.v';
my $nl=new Verilog::Netlist(options=>$opt);
foreach my $file('/home/vp/roopa/i2c/i2c_master_top.v')
   {
     $nl->read_file(filename=>$file);

   }
#read in any sub modules
     $nl->link();
     $nl->lint();
     $nl->exit_if_error();
foreach my $mod($nl->top_modules_sorted)
                {
                show_hier($mod, " ","","");
                }

sub show_hier
{

my $mod=shift;
my $indent=shift;
my $hier =shift;
my $cellname=shift;
if(!$cellname)
{
$hier=$mod->name;
#print "\n",$hier;
}
else
{
$hier.=".$cellname";
}
printf("%45s %s\n",$indent."Module ".$mod->name,$hier);

	foreach my$cell($mod->cells_sorted)
	{
	printf($indent."    Cell %s\n", $cell->name);
	
show_hier($cell->submod,$indent." ", hier,$cell->name) if $cell->submod;
	}
}

##</code><code>##

OUTPUT

Module i2c_master_top i2c_master_top
     Cell byte_controller
                  Module i2c_master_byte_ctrl i2c_master_top.byte_controller
      Cell bit_controller
                   Module i2c_master_bit_ctrl i2c_master_top.byte_controller.bit_controller
     Cell myarbiter
                               Module arbiter i2c_master_top.myarbiter
     Cell mypli1
                                 Module mypli i2c_master_top.mypli1
                                 Module mymux mymux


##</code><code>##

i2c_master_byte_ctrl
i2c_master_bit_ctrl
myarbiter
mypli