&parse_verilog($tool,\%params,\%rm_supply_nets,\%cells); 

sub parse_verilog{    
    my ($tool,$params,$rm_supply_nets,$cells,$cells_hash ) = @_;
        
    my $in_module   = 0;
    my $module;
    
    my $new_cell;

    open(V,$params->{'verilog_in'}) or die "$tool: Error: can't open supplied verilog for reading\n";
    my $line = "";
    while(<V>){	
	chomp();
	next if /^\s*\/\//;
	s/\/\/[\S*||\s*]+$//;  ## chop eol comments
	
	$line .= $_;
	
	

	if(/;\s*$/){ ## indicates end of line.
	    $_ = $line;

	    my @line_arr = split(/\s+/,$_);
	    
	    $line = "";
	    s/\s*;\s*$//;
	    
	    if(/^\s*module/i){
		s/,/ /g;				
		$module = $line_arr[1];		
		$new_cell = new cell ($module);				
		$in_module = 1;
		$new_cell->read_interface($_);	

		next;
	    }   
	}
	if($in_module && /endmodule/i){
	    $cells->{$module} = $new_cell
	    $new_cell = 0;
	    $in_module = 0;		
	    $line = "";
	}
    }
    close(V);    
};