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  clock SDRAM_CLK (fall edge)                                         
+    3.750000   3.750000
  sdram_clk (in)                                                0.1849
+22  0.065438 & 3.815438 f
...
  sd_DQ_out[6] (net)                                  0.475020        
+    0.000000   4.819948 f
  sd_DQ_out[6] (out)                                            0.9991
+21  0.010237 & 4.830185 f
  data arrival time                                                   
+               4.830185

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```
#!/usr/bin/perl 
use strict;
...
```