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PVT === ffg0p82v100c
mnk_alpha ==== VDD 0.825,VDDQN 1.17,VDDM 1.17
...
Missing Bias voltages 
VSS from mnk_alpha file. 
VDD from mnk_lib_ss0p905v100c_pg.lib file

put cornerData(ffg0p82v100c) {VDD 0.825,VDDQN 1.17,VDDM 1.17,TEMP 100}
put cornerData(ssg0p905v100c) {VDD 0.825,VDDQN 1.1,VDDM 0.17,TEMP 100}
put cornerData(tt0p40v100c) {VDD 0.825,VDDQN 1.07,VDDM 2.15,TEMP 100}

library(mnk_lib_ss0p905v100c) {
  voltage_map(VDDQN, 1.1);
...
    }
  }
}

library(mnk_lib_ff0p82v100) {
  voltage_map(VDDQN, 1.1);
...
    }
  }
}

library(mnk_lib_tt0p4v100c) {
  voltage_map(VDDQN, 1.1);
...
    }
  }
}

my $in_macro = $ARGV[0]; 
my $alpha_config = $ARGV[1]; 
...

    }
}