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File1 is as follows....
architecture DEF_ARCH of fulladder_postsyn is 
...

    signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0, VCC_0
         : std_logic;

File2 is as follows..
component XOR2 
...
         B : in std_logic := 'U';
         Y : out std_logic);
end component;