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component MAJ3
...

begin 
enable_pad : INBUF port map (PAD => enable, Y => enable_c);

a_e
b_e
c_e

signal \GND\, \VCC\, N_5, a_c, b_c, c_c, sum_c, GND_0, 

VCC_0, a_e, b_e, c_e, enable_c: std_logic;

open (IN1, "<FA.vhd") or die;
open (OUT, ">common_modify.vhd") or die;
...
close (IN1);
close (OUT);