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INFO @1101994 PHResourceLayer_Z7b: DUMMY:Hi this is CORE2  ; T=1101994
INFO @1102266 PHResourceLayer_Z4: mti_clk_chk:################ start o
+f test ################ ; T=1092507
...
INFO @1148662 END_TESTCASE: Fatals= 0; T=1148662
INFO @1148662 END_TESTCASE:    TESTCASE PASS    ; T=1148662
INFO @1148662 END_TESTCASE: Testcase completed Successfully; T=1148662

INFO @1102372 mti_clk_chk:  Checking period of MTI CLk; T=1102372
INFO @1102377 mti_clk_chk: Period value of MTI Clock: 3.125000 ns; T=1
+102377
...
INFO @1148662 END_TESTCASE: Fatals= 0; T=1148662
INFO @1148662 END_TESTCASE:    TESTCASE PASS    ; T=1148662
INFO @1148662 END_TESTCASE: Testcase completed Successfully; T=1148662

UVM_INFO @1091277 reporter [Z7_COREB]: WR8: A=fc03c002 W=08 R=08; T=10
+91277
UVM_INFO @1091528 reporter [Z7_COREB]: pre_main: Inserting random dela
+y through asm nops, random loop count is  00000009; T=1091528
...
UVM_INFO @1130797 END_SIM: Testcases completed Total= 1; T=1130797
UVM_INFO @1130797 END_SIM: Testcases completed Successfully= 1; T=1130
+797
UVM_INFO @1130797 END_SIM: Testcases with Warnings= 0; T=1130797

 
UVM_INFO @1092598 reporter [testbench.top_level_module.\mti_clk_chk::m
+ain ]:  Checking period of MTI CLk; T=1092598
UVM_INFO @1092605 /proj/rru2_verif/usr/Tilak/SV_UVM/testbench/data_ipd
+ss/v_ms_mti_stim_vip/testbench/classes_v/mti_clk_chk.sv(147) uvm_test
+_top.default_env.default_sequencer[100]@@mti_clk_chk [mti_clk_chk:INF
+O]: Period value of MTI Clock: 3.125000 ns; T=1092605
...
[uvm_test_top.uvm_fuse_load_manager_inst]   215
UVM_INFO @1130797 END_SIM: Testcases completed Total= 1; T=1130797
UVM_INFO @1130797 END_SIM: Testcases completed Successfully= 1; T=1130
+797

Data from LOG1:

...
[uvm_test_top.uvm_fuse_load_manager_inst]   215
UVM_INFO @1130797 END_SIM: Testcases completed Total= 1; T=1130797
UVM_INFO @1130797 END_SIM: Testcases completed Successfully= 1; T=1130
+797