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#!/usr/bin/perl
use Verilog::Netlist;
...
show_hier($cell->submod,$indent." ", hier,$cell->name) if $cell->submo
+d;
    }
}

OUTPUT

...
                                 Module mypli i2c_master_top.mypli1
                                 Module mymux mymux

i2c_master_byte_ctrl
i2c_master_bit_ctrl
myarbiter
mypli