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int mytest3(SV* sv_vec, unsigned int bit) {

...

    return 1;
}

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#define REGSIZE 64
#define TSTVEC( v, b ) v[ b / REGSIZE ] &  ( 1ULL << ( b % REGSIZE ) )
+ )
#define SETVEC( v, b ) v[ b / REGSIZE ] |= ( 1ULL << ( b % REGSIZE ) )
+ )