If i do

my $match = "(?<=module ).*?$ARGV[2].*?([\\(;])";
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Then the output is

//Verilog HDL for "tt", "hh" "functional"
// if i write the word module module NEW(Y, A, B );
    output Y;
    input A;
    input B;

endmodule
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this does not solve the issue :(