reading the article on Locality of Reference on wiki... I guess sundialsvc4 has a point.

No, he doesn't.

In the context of the discussion in this thread -- the effects of locality of reference on the performance of arrays or vectors versus linked-lists -- the salient part of the wiki article is:

Typical memory hierarchy (access times and cache sizes are approximations of typical values used as of 2013 for the purpose of discussion; actual values and actual numbers of levels in the hierarchy vary): CPU registers (8-256 registers) – immediate access, with the speed of the inner most core of the processor

L1 CPU caches (32 KiB to 512 KiB) – fast access, with the speed of the inner most memory bus owned exclusively by each cores

L2 CPU caches (128 KiB to 24 MiB) – slightly slower access, with the speed of the memory bus shared between twins of cores

L3 CPU caches (2 MiB to 32 MiB) – even slower access, with the speed of the memory bus shared between even more cores of the same processor

Main physical memory (RAM) (256 MiB to 64 GiB) – slow access, the speed of which is limited by the spatial distances and general hardware interfaces between the processor and the memory modules on the motherboard

Since people don't appear to have bothered to watch the full video I linked above, here is the salient part of it (7:46). It'd be worth 8 minutes of anyone's time to watch it.