Re^2: how to split file with some pattern (Verilog)

Hi toolic, could I ask a verilog:perl module usage question, how I can use the script to extract all pin in analog_atop instance (as following codes) to analog_atop_io array?

 analog_atop u_analog_atop (.PAD_VDDA ( PAD_VDDA ) , .DPAD_VSSA ( DPAD
+_VSSA )
    , .PAD_VREFADC ( PAD_VREFADC ) , .PAD_ADGPIO_4 ( PAD_ADGPIO_4 )
    , .PAD_ADGPIO_7 ( PAD_ADGPIO_7 ) , .PAD_ADGPIO_5 ( PAD_ADGPIO_5 )
    , .DPAD_VSS_ACMP ( DPAD_VSS_ACMP ) , .DPAD_VSS_PM ( DPAD_VSS_PM )
    , .PAD_VDDADDAC ( PAD_VDDADDAC ) , .PAD_VDDCLK ( PAD_VDDCLK )
    , .DPAD_VSS_XTAL24M ( DPAD_VSS_XTAL24M ) , .DVSS ( GNDD_ON )
    , .DVDD12 ( VDIG_ON ) , .LNA_EN ( n_IP_protect_576 ) , .PAD_XO ( P
+AD_XO )
    , .LNA1_CURSET ( {n_IP_protect_573 , n_IP_protect_572 } )
    , .FILT_MUX_IN_HZ ( n_IP_protect_446 )
    , .FILT_MUX_IN_IQSWAP ( n_IP_protect_447 )
    , .CTL_SYNTH_COARSE_CAL_EN ( n_IP_protect_312 )
    , .PAD_ADGPIO_6 ( PAD_ADGPIO_6 )
    , .SEL_RXMIX_LOBIAS ( {n_IP_protect_864 , n_IP_protect_863 } )
    , .CTL_CXI_XO24M ( {n662 , n447 , n449 , n2478 } )
    , .CTL_SYNTH_EN ( n_IP_protect_313 )
    , .CTL_CXO_XO24M ( {n2705 , n439 , n441 , n443 } ) , .CTL_BBPLL_EN
+ ( n2303 )
    , .CTL_BBPLL_DIV_RXADC ( {n540 , n1230 } )
    , .CSR_BBPLL_CORE_GC ( {n516 , n403 , n1224 , n_IP_protect_104 , n
+517 ,
        n_IP_protect_102 , n_IP_protect_101 , n_IP_protect_100 } )
    , .CSR_BBPLL_TEST_GC ( {n_IP_protect_124 , n416 , n_IP_protect_122
+ , n509 , n417 , n511 ,
        n_IP_protect_117 , n1213 , n512 , n_IP_protect_114,        n_I
+P_protect_113 , n513 , n406 , n514 , n_IP_protect_131 , n531 ,
        n532 , n533 , n_IP_protect_127 , n398 , n409 , n410 , n515 ,
        n_IP_protect_108 } ) );
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Re^3: how to split file with some pattern (Verilog) by toolic (Bishop) on Jan 26, 2015 at 02:22 UTC
Some nodes which may help: Re^3: verilog perl usage (Verilog::Netlist) SuperSearch where title contains "verilog"... hit "search" button	[reply]
Re^4: how to split file with some pattern (Verilog) by herman4016 (Acolyte) on Jan 26, 2015 at 10:10 UTC
i try the following codes but i got the error, please help! %Error: ./soc.post.PG.simple.v:9313: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:8877: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:9305: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:9277: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:10744: Module/Program/Interface referen +ce not found: MUX2ND2BWP7THVT %Error: ./soc.post.PG.simple.v:10281: Module/Program/Interface referen +ce not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:9473: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:10634: Module/Program/Interface referen +ce not found: BUFFD4BWP7THVT %Error: ./soc.post.PG.simple.v:11134: Module/Program/Interface referen +ce not found: BUFFD4BWP7THVT %Error: ./soc.post.PG.simple.v:8193: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:10073: Module/Program/Interface referen +ce not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:8137: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:11016: Module/Program/Interface referen +ce not found: INVD4BWP7THVT %Error: ./soc.post.PG.simple.v:10516: Module/Program/Interface referen +ce not found: INVD4BWP7THVT %Error: ./soc.post.PG.simple.v:8761: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:11358: Module/Program/Interface referen +ce not found: TIELBWP7THVT %Error: ./soc.post.PG.simple.v:9053: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT %Error: ./soc.post.PG.simple.v:8629: Module/Program/Interface referenc +e not found: HDRDID2BWP7THVT [download] `#!/usr/bin/perl use strict; use warnings; use Verilog::Netlist; # prepare netlist my $nl = new Verilog::Netlist(); $nl->read_file(filename => './soc.post.PG.simple.v'); # read in any sub modules $nl->link(); $nl->lint(); $nl->exit_if_error(); my $module = $nl->find_module("soc"); $module->link(); $module->lint(); $module->exit_if_error(); print ''.$module->name."\n";` [download]	[reply] [d/l] [select]
Re^5: how to split file with some pattern (Verilog) by toolic (Bishop) on Jan 26, 2015 at 13:24 UTC
I can't reproduce your problem because I don't have your input file. Debugging 101: remove most of the code from your input file until it passes, then start adding code back in until you identify your problem.	[reply]