Hi toolic, that is great you speak Verilog. May be, I can seek some help with my hash described below from the original code :)

Here is a very basic question I have. Perhaps, I did not ask the core of my question earlier, correctly and got lost in the details:

In lines 47 through 49, I have the following code, where I am printing keys:

 47    foreach my $signal (keys %{$inTimeRangeSignalsH{$vcdFile}}) {
 48     print "Line 48 ::Dbg:: $signal $vcdFile\n";
 49    }
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Further down in my code in lines 61 through 65, I am again printing the same keys and expecting that I get the same keys are the result (order of results is not important).

But unfortunately, that expectation does not seem to be true.

Why are the keys from the same hash different, when printed using lines 48 through 49 and lines 61 through 65?

 61  foreach my $vcdFile (keys %inTimeRangeSignalsH) {
 62   foreach my $sig (keys %{$inTimeRangeSignalsH{$vcdFile}}) {
 63    print "Line 63 ::Dbg:: $sig $vcdFile\n";
 64   }
 65  }
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Any insights/corrections will be a great help.