Parsing Verilog files can be tricky, and you should probably use a parser: Verilog-Perl. But, this might work for simple files:

use warnings;
use strict;

# Change input record separator to parse whole Verilog lines
local $/ = ';';
while (<DATA>) {
    s/\s+/ /g;    # Convert all whitespace to single-space
    print "$_\n";
}

__DATA__
 DFFX1 k0_reg_184  ( .D(key_184 ), .CLK(clk), .QN(n18736) );
DFFX1 k0_reg_183  ( .D(key_183 ), .CLK(clk), .Q(k0_183 ), .QN(n65993)
         );
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Output:

 DFFX1 k0_reg_184 ( .D(key_184 ), .CLK(clk), .QN(n18736) );
 DFFX1 k0_reg_183 ( .D(key_183 ), .CLK(clk), .Q(k0_183 ), .QN(n65993) 
+);
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