in reply to Help with deciding on module namespace (Verilog::VCD::* ?)
($q=q:Sq=~/;[c](.)(.)/;chr(-||-|5+lengthSq)`"S|oS2"`map{chr |+ord }map{substrSq`S_+|`|}3E|-|`7**2-3:)=~y+S|`+$1,++print+eval$q,q,a,
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Re^2: Help with deciding on module namespace (Verilog::VCD::* ?)
by vijayvithal (Novice) on May 19, 2017 at 17:12 UTC |