princepawn you disappoint me. I used to be impressed by the clear thinking in your arguements. Nobody said that a CISC set would run well on a RISC machine. If you find someone claiming that, please post a link because I would be fascinated to see the reasons for someone claiming it. However the stated reason for a CISC VM with lots of registers is that there the VM shouldn't be crippled by bad Intel design decisions. I don't recall RISC being mentioned specifically, and I think it's fairly obvious that RISC machines are just going to have to keep up as best they can.

Does it make any sense to create a low-level machine modeled on one-architecture instead of a high-level architecture which can flexibly optimize to either architecture?

In case you missed my last paragraph, the stated intent of the parrot developers is to create a medium-to-low-level architecture that can be optimised in a machine-specific way. Why didn't you read the stated intent of the developers? You put words into their mouths-the wrong words.

Given that the proposed "low-level" architecture is probably too low for flexible optimization,

Register based machines were chosen because of the large amount of literature on optimising register based machines. Now if you read posts by the developers (as you clearly haven't), they plan to do much optimisation in the parse tree, and then save the source code along with the byte code for chances at further optimisation. You didn't read that bit, did you?

Also, I thought Parrot was not "stack-based" If that is the case then why does Overview.pod say this:

Register based machines have stacks. You don't actually know anything at all about assembler or machine design, do you?

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Jeremy
I didn't believe in evil until I dated it.