Hi sid.verycool
Using the data set you provided,

• you could use lookahead assertion like so:

  use warnings;
  use strict;
  
  while (<DATA>) {
      chomp;
      s/(.+?)OLD(?=\()/$1NEW/; 
      print $_, $/;
  }
  
  __DATA__
   //Verilog HDL for "tt", "hh" "functional"
  // if i write the word module here the script goofs up
  `timescale 1ps/10fs
  
  
  module OLD(Y, A, B );
      output Y;
      input A;
      input B;
  
  endmodule
  [download]

• you can also use the wisdom of CountZero

  while (<DATA>) {
      chomp;
      s/(.+?)OLD/$1NEW/ unless m{//};
      print $_, $/;
  }
  
  __DATA__
   //Verilog HDL for "tt", "hh" "functional"
  // if i write the word module here the script goofs up
  `timescale 1ps/10fs
  
  
  module OLD(Y, A, B );
      output Y;
      input A;
      input B;
  
  endmodule
  [download]

 //Verilog HDL for "tt", "hh" "functional"
// if i write the word module here the script goofs up
`timescale 1ps/10fs


module NEW(Y, A, B );
    output Y;
    input A;
    input B;

endmodule
[download]