Yes, this is a state machine. I spend a lot of time coding in Verilog, where toggling a bit is a natural part of the language. I guess this would be cleaner in Perl: 
    $out = $out ? 0 : 1 if $_ eq '"';

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I do not know why Perl sets $out to undef.

In reply to Re^3: In place replace, ignoring between quotes by toolic
in thread In place replace, ignoring between quotes by Klainn

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