Well, this is curious. Intel reference has this about prefetchtx:

Fetches the line of data from memory that contains the byte specified with the source operand to a location in the cache hierarchy specified by locality hint.
There's no need to align the prefetch pointer. Be sure to align the data records themselves, of course.

I run a little pointer-chasing bench (on Nehalem). The optimum appears to be fetching ~16 links ahead. But this is just an empirical point. You could try increasing the prefetch distance.

There's a LOAD_HIT_PRE event that indicates too-late prefetches, might try that. Also, it helps to see clocks together with UOPS_RETIRED (or INST_RETIRED), to see whether it does a lot of work or a lot of stalling. Branch mispredictions may also show up there.

Update.

One article gives these figures for Haswell: 10 line fill buffers, 16 outstanding L2 misses. Prefetch hints that can't be tracked are simply dropped. There are also hardware prefetcher units that detect "streams" of consecutive requests in same direction. So yes, the order of memory accesses (prefetches too?) can make a difference.

Intel has some docs on tuning. Your loop could be improved in many ways, but don't get carried away. Figure out how you can lookup q8+q9 together, eliminating two inner loops.

In reply to Re^5: The 10**21 Problem (Part 3) by oiskuu
in thread The 10**21 Problem (Part 3) by eyepopslikeamosquito

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