Hello Monks,

I have written a perl code which can merge two files according to the need. Now the intention is, the updated script should work for any number number of input files. The current script expects two input files to progress.

Let me explain you what the script is actually doing. The current script (please refer the code below) expects two input files, (please refer file_1 and file_2). The common part for both file_1 and file_2 is the header section. So the script

1. Will delete the header section from file_2.

2. Will merge updated file_2 with file_1 after deleting the last line (or should say, the " { " character from the last line from file_1 ).

Now the same process must go on for the extra provided inputs for the updated scripts. Can you folks please help me?

perl code

#!/usr/bin/perl
use strict;
use warnings;

my $inputfile_one = $ARGV[0]; # input lib FILE
my $inputfile_two = $ARGV[1]; # input lib FILE
my $pin_name;
my $counter = 0;

if ($#ARGV!=1)
{
   print "USAGE :: perl lib_marge.pl <<MAIN_LIB_FILE>>  <<LIB_FILE_FOR
+_MARGE>> \n\n" ;
   exit(1);   
}

mkdir 'tmpdir' unless -d 'tmpdir';
mkdir 'finallib' unless -d 'finallib';


my $cmd_1 = "head -n -1  $inputfile_one > tmpdir/$inputfile_one ;"; # 
+Removing the last line from the main lib file
system ($cmd_1);


open (INFILE_TWO,"<","$inputfile_two") || die "Can not open LIB_FILE_F
+OR_MARGE";
open (OFILE,">","tmpdir/Output.csv") || die "Can not open Input Text F
+ile";

  while (my $line = <INFILE_TWO>) {
    chomp $line;
   # print "$line \n";

   if ($line =~m/^\s*cell\s*\(\"(.*)\"\)/g || $line =~m/^\s*cell\((.*)
+\)/g || $line =~m/^\s*cell\s*\((.*)\)/g) {
       $pin_name = $1;
       chomp $pin_name;
       $counter = 1;
   }

   if ( $counter == 1 ) {
    print OFILE "$line\n";
    }

}
close INFILE_TWO;
close OFILE;

my $cmd_2 = "cat tmpdir/$inputfile_one tmpdir/Output.csv > finallib/$i
+nputfile_one ;rm -rf tmpdir";
system ($cmd_2);
[download]

file_1

library ("inv_add") {
  delay_model : lookup_table ;
  date : "Thu Jun  6 07:25:32 2019" ;
  lu_table_template (finc_valc) 
  cell (lib_1) {
    dont_use : true ;
    dont_touch : true ;

    pin ("HIZIBI_IN_1") {
      direction : input ;
      clock : true ;
      max_transition : 1 ;
      capacitance : 12 ;
    }  
    pin ("HIZIBI_79")    {
      direction : output ;
      max_transition : 10;
      min_capacitance : 3 ;
    }              
    pin ("HIZIBI_IN_1") {
      direction : input ;
      clock : true ;
      max_transition : 1 ;
      capacitance : 1 ;
    }  
    pin ("HIZIBI_78")    {
      direction : output ;
      max_transition : 10;
      min_capacitance : 34 ;
      capacitance : 34 ;
    }            
    pin ("HIZIBI")    {
      direction : output ;
      clock : true ;
      max_transition : 20;
      related_power_pin : VDD ;
      related_ground_pin : VSS ;
      timing () {
        cell_fall (into_f1) {
          index_1("1,2,3,4,5") ;
          index_2("1,2,3,4,5") ;
          values("13, 13, 14, 16, 18",\
                 "13, 14, 15, 16, 19",\
                 "14, 15, 16, 17, 20",\
                 "15, 15, 16, 18, 20",\
                 "15, 16, 17, 18, 21") ;
        }  
      }  
    }
  }
}
[download]

file_2

library ("inv_add") {
  delay_model : lookup_table ;
  date : "Thu Jun  6 07:25:32 2019" ;
  lu_table_template (finc_valc) 
  cell (lib_2) {
    dont_use : true ;
    dont_touch : true ;

    pin ("HIZIBI_98")    {
      direction : output ;
      max_transition : 10;
      min_capacitance : 34 ;
      capacitance : 34 ;
    }            
  }
}
[download]

the output file should look like

library ("inv_add") {
  delay_model : lookup_table ;
  date : "Thu Jun  6 07:25:32 2019" ;
  lu_table_template (finc_valc) 
  cell (lib_1) {
    dont_use : true ;
    dont_touch : true ;

    pin ("HIZIBI_IN_1") {
      direction : input ;
      clock : true ;
      max_transition : 1 ;
      capacitance : 12 ;
    }  
    pin ("HIZIBI_79")    {
      direction : output ;
      max_transition : 10;
      min_capacitance : 3 ;
    }              
    pin ("HIZIBI_IN_1") {
      direction : input ;
      clock : true ;
      max_transition : 1 ;
      capacitance : 1 ;
    }  
    pin ("HIZIBI_78")    {
      direction : output ;
      max_transition : 10;
      min_capacitance : 34 ;
      capacitance : 34 ;
    }            
    pin ("HIZIBI")    {
      direction : output ;
      clock : true ;
      max_transition : 20;
      related_power_pin : VDD ;
      related_ground_pin : VSS ;
      timing () {
        cell_fall (into_f1) {
          index_1("1,2,3,4,5") ;
          index_2("1,2,3,4,5") ;
          values("13, 13, 14, 16, 18",\
                 "13, 14, 15, 16, 19",\
                 "14, 15, 16, 17, 20",\
                 "15, 15, 16, 18, 20",\
                 "15, 16, 17, 18, 21") ;
        }  
      }  
    }
  }
  cell (lib_2) {
    dont_use : true ;
    dont_touch : true ;

    pin ("HIZIBI_98")    {
      direction : output ;
      max_transition : 10;
      min_capacitance : 34 ;
      capacitance : 34 ;
    }            
  }
}
[download]

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