However, given your simple input, this script I created 13 years ago should do the trick. It also supports SystemVerilog classes, and it warns about some compiler directives:
=head1 NAME B<hdl_splitlib> - Split up a single Verilog library file into several +files =head1 SYNOPSIS hdl_splitlib file ... =head1 DESCRIPTION Split up a single Verilog library file into several files. Each outpu +t file will contain a single C<module> or C<class>. Input is a file (or files). Output is written to the current directory (several files). Some warning messages may be sent to STDOUT. Known limitations: - `endcelldefine or `undef compiler directives may follow endmodul +e - Those pesky `define macros!! - module/class definitions which are commented out Example: hdl_splitlib lib.v =cut use warnings FATAL => 'all'; use strict; my $directives_found = 0; my $out = 'temp.v'; my $fh; my $modname; open $fh, '>', $out; while (<>) { print $fh $_; if (/^\s*end(?:module|class)\b/) { close $fh; rename $out, "$modname.v"; open $fh, '>', $out; } elsif (/^\s*(?:module|class)\s+(\w+)/) { $modname = $1; } if (/`(define|celldefine|undef)/) { # ` $directives_found = 1; print; } } if ($directives_found) { print "\nWarning. The input file may contain problematic compiler +"; print " directives (define, undef, celldefine).\n\n"; } unless (-z $out) { print "\nWarning. All lines after the last 'endmodule' "; print "line in the input file have been deleted. These "; print "should have only been comments.\n\n"; } unlink $out;
In reply to Re: how to split file with some pattern (Verilog)
by toolic
in thread how to split file with some pattern
by herman4016
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