(Also posted on Stackoverflow, with suboptimal results and at least one deleted answer so far.)

I have a Makefile like this:

default: exe

%.obj: %.src
        # dummy compiler
        @echo link $< to $@
        cat $< > $@

exe: main.obj foo.obj bar.obj
        # dummy linker
        @echo link $^ to $@
        cat $^ > $@

main.obj: main.src

foo.obj: /some/dir/1/foo.src

bar.obj: /some/dir/2/bar.src

[download]

Make can't compile foo.obj and bar.obj (and 20+ other objects), because it does not use the %.obj: %.src rule. The directories of foo.obj and foo.src resp. bar.obj and bar.src do not match, so the rule does not match.

To make that Makefile work, I copied the compiler lines from the pattern rule to the foo.obj and bar.obj rules (and the 20+ other object rules). That's anything but clean and maintainable. Using a canned receipe shortens the copied receipe, but it is still a copy. I don't want to repeat myself. make should be smart enough to find a receipe to compile *.src to *.obj, no matter where those files are.

Essentially, I need a pattern rule that ignores the source and object directories when comparing.

Why, oh why, am I doing this?

foo.src and friends are scattered across a big third-party "SDK" directory tree that is NOT part of the source code in the directory with the Makefile. (Think of it as a christmas tree with a lot of candles. Ripping off the candles is a no-no, as is spraying a few liters of highly flameable liquid onto the tree.) If you want to compile software using the SDK, you are expected to compile the required SDK source files and link them with your code. Note that there are many more source files than really needed, so compiling and linking all of them causes a lot of conflicts and extra compile time. Ultimately, linking will fail.

Alexander

--
Today I will gladly share my knowledge and experience, for there are no sweeter words than "I told you so". ;-)

In reply to [OT] Making GNU make do what I mean by afoken

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