How do you extract the values/attributes from all the XML tags using Perl and output them once Example XML

<Root>
    <tags>
        <first name="AA">
            <A1 name="A"/>
            <B1 name="B"/>
        </first>
        <second name="BB">
            <A1 name="A"/>
            <B1 name="B"/>
            <C1 name="C"/>
        </second>
        <Third name="CC">
            <A1 name="A"/>
            <B1 name="B"/>
            <C1 name="C/>
        </Third>
        <Fourth name="DD">
            <A1 name="A"/>
            <B1 name="B/>
            <C1 name="C/>
        </Fourth>
     </tags>
<Root>

[download]

Output: I just need the output which is: 

A
B
C

[download]
Any help is appreciated Note:I'm using XML::Simple, I know XML::Simple is not that easy. Kindly do post a example code just for reference. Because I'm unclear where to start

Original node content restored above by GrandFather

how to declare wires for verilog using perl. The XML data has the following information for modules which is needed Example XML

<Root>
    <tags>
        <Module ="AA">
            <Input name="cpu_control"/>
            <Output name="power_control"/>
        </first>
        <module="BB">
            <Input name="data_b"/>
            <output name="data_out"/>
            <bidirection name="add_bus"/>
        </second>
        <Module="CC">
            <Input name="power_con"/>
            <Bidirection name="data_b"/>
        </Third>
      </tags>
</Root>

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I'm trying to generate a wire declaration for verilog using perl scripting. I however have an idea on how to do it, but less clue on implementing it. The Idea I have is, "foreach lower module the signals of inputs, outputs, inouts(bidirection) if not present in the top module then these should be declared as wires." 

sample output:
wire  power_control;
wire  add_bus;
wire  cpu_control;

[download]
My code

use warnings;
use XML::Simple;
use Data::Dumper;

my $xml=XMLin('sample.xml');
my $roottags=$xml->{tags};
my $topmodule=$roottags->{Module};
my @mod=keys %$topmodule;

foreach my $modules(values %$topmodule)
{
    my $modu_temp=shift(@mod);
    #print "$modu_temp\n";
#my $ins_mod=$modules->{input};
     my @ins=(keys %{$modules->{input}});
     if(exists $ins[0]){}
     else{
     $in_1=$modules->{input};
     @ins=$in_1->{name};
     }
    print @ins, "\n";
   }

[download]

Is my logic close enough? because I get the output which I dont want

Any help is appreciated Note:I'm using XML::Simple, I know XML::Simple is not that easy. Kindly do post a example code just for reference. Because I'm unclear where to start

In reply to Extract attributes/values from XML using perl / declaring wires in verilog using perl by gr.d

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