Hello All,

I am trying to write a perl code which will do the following task.

The code will read two .lib file, ref_lib.lib and org_lib.lib. After doing the operations it will dump final_lib/org_lib.lib.

From ref_lib.lib it will only read the lines from "cell(" ( everything in between) to "leakage_power". And whatever it is reading from ref_lib.lib will be stored in a variable, say $attr_org.

Similarly it will also read org_lib.lib. Now the code will dump everything, from line1 of org_lib.lib to final_lib/org_lib.lib, except the lines in between "cell(" and "leakage_power". This lines will be replaced by $attr_org.

The structure of final_lib/org_lib.lib are also given below.

I tried to write the code but can not understand where it is going wrong.

Can you folks please let me know what change should be in the code? 

# Staring of perl code attr_update.pl
my $ref_lib = $ARGV[0];
my $org_lib = $ARGV[1];

my $cell_flag = 0;
my $lkg_flag = 0;
my $attr_org;
my $cell_name_ref;
my $cell_name_org;

system "rm -rf final_lib";
system "mkdir final_lib";

if ($#ARGV !=1) {
  print STDERR "Usage of script: perl attr_update.pl <REF_LIB> <ORG_LI
+B> \n" ;
  
}


open (REFLIB,"<","$ref_lib") || die "Can not open REF_LIB" ;
open (ORGLIB,"<","$org_lib") || die "Can not open ORG_LIB" ;
open (FINALLIB,">","final_lib/$org_lib") || die "Can not open ORG_LIB"
+ ;


 while (my $line = <REFLIB>) {
   chomp($line);
   #print "$line \n";
    if ($line=~m/^\s*cell\(.*/g){
     $cell_flag = 1;
     $lkg_flag = 0;
     $cell_name_ref = $line;
     #print "OK 1\n";
     }
    
#<STDIN>
    if ($line=~m/^\s*leakage_power\(\)/g){
     $cell_flag = 0;
     $lkg_flag = 1;
    }   


    if (($cell_flag ==1) && ($lkg_flag == 0)){
      $attr_org = $line;
      #print "$attr_org \n";
    }

    while (my $line_2 = <ORGLIB> ){
     chomp ($line_2);
      
      if ($line_2=~m/^\s*cell\(.*/g){
       $cell_name_org = $line_2;
      }
      
      if ($cell_name_ref == $cell_name_org){
       print FINALLIB "$attr_org \n";
      }
      
      else {
        print FINALLIB "$line_2 \n";
     
      }
    }
 }

[download]
##Staring of ref_lib.lib
library_for_dev_47nm_proj {


             cell(and2_f2) {
              area : 434.7;
          cell_type : combo;
          cell_function : A * B;
          timing_const : NIL;
          clock_present : NIL;
          
              leakage_power() {         
              power_pin : "VDD" ;         
              when : "!A&!B" ;         
              value : "0.000047" ;         
              }        
          
              pin(A1) {
                 direction : input;
                 capacitance : 2.141;
                }

              pin(Y) {
                 direction : output;
                 function : "A1 * B1";

                }
             }


             cell(nand2_f2) {
          area : 359.1;
          cell_type : combo;
          cell_function :(A1 * B1)\u201;
          timing_const : NIL;
          clock_present : NIL;

              leakage_power() {         
              power_pin : "VDD" ;         
              when : "!A&B" ;         
              value : "0.00057" ;         
              }        
           
               pin(A1) {
               direction : input;
               capacitance : 12.547;
              }
              
          pin(B1) {
                direction : input;
                capacitance : 12.259;
              }
              
          pin(O) {
                direction : output;
                function : "(A1 * B1)\u2019";
              }
           }

             cell(dfr_f5) {
              area : 4819.5;
          cell_type : seq;
          cell_function : d=!q;
          timing_const : YES;
          clock_present : YES;

              leakage_power() {         
               power_pin : "VDD" ;         
               when : "D" ;         
               value : "5.00057" ;         
              }        

               
             pin(Q) {
                   direction : output;
                   function : "IQ";
               }
            }

 }

[download]
##Staring of org_lib.lib

library_for_dev_47nm_proj {

lu_table_template(t4x3) {
   variable_1: total_output_net_capacitance ;
   variable_2: input_net_transistion ;
   index_1 {\u201c5, 20, 60, 200\u201d} ;
   index_2 {\u201c0.01, 0.1, 2.0\u201d} ;
 }

            cell(and2_f2) {
          cell_type : combo;
          cell_function : A * B;
          timing_const : NIL;
          clock_present : NIL;
          
              leakage_power() {         
              power_pin : "VDD" ;         
              when : "!A&!B" ;         
              value : "0.000047" ;         
              }        
          
              pin(A1) {
                 direction : input;
                 capacitance : 2.141;
              }
              pin(B1) {
                 direction : input;
                 capacitance : 1.948;
              }
              pin(Y) {
                 direction : output;
                 function : "A1 * B1";

                }
             }


             cell(nand2_f2) {
          area : 359.1;
          cell_type : combo;
          cell_function : (A1 * B1)\u201;
          clock_present : NIL;
           
              leakage_power() {         
              power_pin : "VDD" ;         
              when : "!A&B" ;         
              value : "0.00057" ;         
              }        

              pin(A1) {
               direction : input;
               capacitance : 12.547;
              }
              
          pin(B1) {
                direction : input;
                capacitance : 12.259;
              }
              
          pin(O) {
                direction : output;
                function : "(A1 * B1)\u2019";
              }
           }

             cell(dfr_f5) {
               area : 4819.5;
           timing_const : YES;
           clock_present : YES;

              leakage_power() {         
               power_pin : "VDD" ;         
               when : "D" ;         
               value : "5.00057" ;         
              }        

              ff(IQ,IQN) {
                   next_state : "DATA1";
                   clocked_on : "CLK2\u2019";
                   clear : "RST3\u2019";
               }
               pin(DATA1) {
                   direction : input;
                   capacitance : 51.289;
                 }
               pin(CLK2) {
                   direction : input;
                   capacitance : 52.305;
               }
               pin(RST3) {
                   direction : input;
                   capacitance : 28.602;
               }
             pin(Q) {
                   direction : output;
                   function : "IQ";
               }
            }

 }

[download]
##Staring of final_lib/org_lib.lib


library_for_dev_47nm_proj {

lu_table_template(t4x3) {
   variable_1: total_output_net_capacitance ;
   variable_2: input_net_transistion ;
   index_1 {\u201c5, 20, 60, 200\u201d} ;
   index_2 {\u201c0.01, 0.1, 2.0\u201d} ;
 }

            cell(and2_f2) {
              area : 434.7;
          cell_type : combo;
          cell_function : A * B;
          timing_const : NIL;
          clock_present : NIL;
          
              leakage_power() {         
              power_pin : "VDD" ;         
              when : "!A&!B" ;         
              value : "0.000047" ;         
              }        
          
              pin(A1) {
                 direction : input;
                 capacitance : 2.141;
              }
              pin(B1) {
                 direction : input;
                 capacitance : 1.948;
              }
              pin(Y) {
                 direction : output;
                 function : "A1 * B1";

                }
             }


             cell(nand2_f2) {
          area : 359.1;
          cell_type : combo;
          cell_function : (A1 * B1)\u201;
          timing_const : NIL;
          clock_present : NIL;
           
              leakage_power() {         
              power_pin : "VDD" ;         
              when : "!A&B" ;         
              value : "0.00057" ;         
              }        

              pin(A1) {
               direction : input;
               capacitance : 12.547;
              }
              
          pin(B1) {
                direction : input;
                capacitance : 12.259;
              }
              
          pin(O) {
                direction : output;
                function : "(A1 * B1)\u2019";
              }
           }

             cell(dfr_f5) {
               area : 4819.5;
           cell_type : seq;
           cell_function : d=!q;
           timing_const : YES;
           clock_present : YES;

              leakage_power() {         
               power_pin : "VDD" ;         
               when : "D" ;         
               value : "5.00057" ;         
              }        

               ff(IQ,IQN) {
                   next_state : "DATA1";
                   clocked_on : "CLK2\u2019";
                   clear : "RST3\u2019";
               }
               pin(DATA1) {
                   direction : input;
                   capacitance : 51.289;
                 }
               pin(CLK2) {
                   direction : input;
                   capacitance : 52.305;
               }
               pin(RST3) {
                   direction : input;
                   capacitance : 28.602;
               }
             pin(Q) {
                   direction : output;
                   function : "IQ";
               }
            }

 }

[download]

In reply to Selective lines updation from one file (file1) to another (file2) without changing the rest of the sections to a new fine($dir/file2) by anirbanphys

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