vppreproc has a +define+ option. Did you try that?

veripool also offers emacs verilog mode. I don't use emacs, but I think it has some capabilities for stitching modules together.

You can use Super Search to look for Verilog-Perl code examples I've posted here at the Monastery. I always add "Verilog" to the titles. What tokens can't you get? Post a tiny example of your Perl code plus your Verilog input file.

In reply to Re: how to preserve `defines in verilog -perl by toolic
in thread how to preserve `defines in verilog -perl by justrajdeep

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