I am unable to get where the `ifdef is defined.
You need to clarify what you're looking for. This is what I get when I run your code: 
  Module top                                  top
      Cell b0
    Module buff                               top.b0
         input buf_in
         inoutput out
        Cell i0
         .in(buf_in)
         .out(a)
      Module inv                              top.b0.i0
           input in
           output out
        Cell i1
         .in(a)
         .out(buf_out)
      Module inv                              top.b0.i1
           input in

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What output do you expect to get?

Keep in mind that there is a forum on veripool.

In reply to Re^3: how to preserve `defines in verilog -perl by toolic
in thread how to preserve `defines in verilog -perl by justrajdeep

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