G'day manchali,

Welcome to the Monastery.

Firstly, I'll let you know upfront that I don't know about Verilog so I probably can't provide any direct help. Having said that, I have seen it discussed here previously, so there are other monks who probably can help. I'll front-page your question to give it a bit more exposure and to avoid it falling off the radar over the weekend: you may have to wait until next week until someone knowledgeable gets around to reading it.

I did have a look at the documentation for Verilog-Perl. Have you read this? Can you formulate a more specific question based on this? The link to vrename looked promising. Its description starts:

"Vrename will allow a signal to be changed across all levels of the design hierarchy, or to create a cross reference of signal names. (It actually includes module names, macros, and other definitions, so those can be changed too.)"

Is that any help to you?

And, as haukex has already indicated, the more information you provide, the better the help we can provide. Please do follow the links he provided.

— Ken

In reply to Re: Connection mapping between signals of logical heirarchy by kcott
in thread Connection mapping between signals of logical heirarchy by manchali

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