Your input file looks like Verilog, except that Verilog requires the keywords to be lower-case. If so, you can use the Verilog::Netlist parser to read the file and get all the signals you need. This is preferable to rolling your own parser, which can be difficult. 
use warnings;
use strict;
use Data::Dumper        qw(Dumper);
use Verilog::Netlist    qw();
use File::Slurp         qw(write_file read_file);

my $file = shift;

# Create a temporary file with lower-case keywords
my @lines;
for (read_file($file)) {
    s/(\w+)/lc $1/e;
    push @lines, $_
}
write_file('temp', @lines);

my $nl = Verilog::Netlist->new();
$nl->read_file(filename => 'temp');
$nl->exit_if_error();
my %sigs;
my @wires;
for my $mod ($nl->top_modules_sorted()) {
    print 'mod=', $mod->name, "\n";
    for my $sig ($mod->nets()) {
        push @wires, $sig->name;
    }
    for my $sig ($mod->ports_sorted()) {
        my $dir = $sig->direction();
        $dir .= 'put' unless $dir eq 'inout';
        my $name = $sig->name();
        $sigs{$name} = {dir => $dir};
    }
    for my $cell ($mod->cells_sorted) {
        printf "    Cell %s\n", $cell->name;
        for my $pin ($cell->pins_sorted) {
            printf "     %s\n", $pin->netname;
        }
    }
}

print Dumper(\%sigs);
print Dumper(\@wires);

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In reply to Re: Output not correct (Verilog::Netlist) by toolic
in thread Output not correct by nursyza

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