A number of additional points:

I added some keywords to the title of this node because it is quite relevant to my line of work, and I know I will want to refer back to it in the future. When I ran a SuperSearch on "Verilog" and/or "SDF", this node was not located. Of course, I linked to this node, but maybe others will be able to locate it more easily now.

The syntax of the code in the OP is specified in the IEEE Standard 1497-2001 document, titled: 

IEEE Standard for Standard Delay Format (SDF)
for the Electronic Design Process

[download]
I'm mentioning this just in case anyone following this stream was wondering what this strange syntax was. It is used by digital IC hardware designers who use the Verilog language.

I like BrowserUK's solution. In the SDF syntax, to quote the spec: "White space is never significant except when used within quoted strings or to separate lexical tokens." So, end parentheses need not be on separate lines. We have had the need to hack an SDF file, similar to what the OP poster has done, but our solution is pretty nasty. At some point, I will probably give this a try.

I am one of those who upvoted shoness's node because that may well be the best solution for the OP. It is too bad the the OP has not responded to this node, because there may be additional solutions which could be offered if these few basic questions were answered.

That being said, we have decided that hacking our SDF file is the most cost-effective solution, given our circumstances. We do disable timing checks using simulator options, but we have other constraints which make it difficult to disable them for all cells. We should extend our own cell library to handle this case, but that takes more time and resources than hacking the SDF file.

Thanks to all for contributing to this very useful (at least to me) thread. I'm usually not this long-winded, so I'll shut up now.

In reply to Re^4: Comment a block that match a keyword (Verilog SDF) by toolic
in thread Comment a block that match a keyword by yorkwu

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