You will suffer greatly if you try to write your own general Verilog parser.

There are modules on CPAN that can do it for you. Maybe Verilog::Parser or Verilog::SigParser?

If you need to parse some auto-generated file or a restricted subset of the language, you stand a better chance. Is your example data auto-generated? Who but a machine would omit the carriage return following the ";" before the always block?

I don't know what you want to DO with the always block (and the rest of that Verilog code). What are you building in Perl and what data do you want to collect from the code to make it happen?

For your example code block, it is straightforward to pull out the clock, the reset (and it's polarity) and the expression this DFF uses. The next always block might be a latch, or a flop with synchronous reset, or no reset, or have multiple signals, or use SystemVerilog always_ff, or be an entire state-machine, or call a task, etc. In short, you need a language parser.

My advice is to use, or build on, what exists if possible. If not, then restrict what you are doing and start small.

In reply to Re: Reading block by shoness
in thread Reading block by ravi030

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